Code Position Modulation (CPM) is used as the modulation format for the IEEE 802.15.4 standard, IEEE std. 802.15.4-2003, published Oct. 1, 2003, for low-rate wireless personal area networks (WPAN's), and for Cypress WirelessUSB™ standard. Size, cost, and power consumption are important parameters for devices within these standards. CPM is a variant of Direct Sequence Spread Spectrum (DSSS) modulation, in which data to be transmitted is encoded not as a single PN code sequence, but as one of several bit-shifted derivatives of a single PN code sequence. DSSS generates a redundant bit pattern for each bit to be transmitted. This bit pattern is called a pseudo noise (PN) code. The PN code is a binary signal that is produced at a much higher frequency than the data that is to be transmitted. Because it has a higher frequency, it has a large bandwidth that spreads the signal in the frequency domain (i.e., it spreads its spectrum). The nature of this signal makes it appear that it is random noise. The wide bandwidth provided by the PN code allows the signal power to drop below the noise threshold without losing any information. This allows DSSS signals to operate in noise environments and reduces the interference caused by conventional narrowband signals. The longer the PN code is, the greater the probability that the original data can be recovered.
In CPM, each transmitted symbol is represented by an N-chip PN code (e.g., code sequence or PN code), where k bits of information can be encoded into each symbol by circularly shifting the N-chip PN code to one of 2^k positions (where 2^k is less than or equal to N).
Conventional implementations of CPM systems have used quadrature phase shift key (QPSK) radio frequency (RF) modulation. In these conventional implementations, the CPM code sequence is encoded in one phase pair of the QPSK, and a clock signal is encoded in the other phase pair. This may allow the receiver to be self-clocking, where a change in phase in the clock phase pair is used to clock in a data chip represented by the phase state of the other phase pair. Binary phase shift key (BPSK) and frequency shift key (FSK) are examples of RF modulation techniques, which are simpler and smaller to implement than QPSK. These modulation techniques also typically allow the design of lower power receiver circuits than receiver circuits implementing QPSK.
Conventional methods for generating the circularly shifted symbol include the use of a look-up table that contains the N-chip PN code sequences for each of the 2^k required shifts. This requires a large amount of memory for large values of k. Another conventional method uses a circular shift register and a down-counter. The down-counter is loaded with the shift value, and the shift register is shifted once for each count of the down-counter. When the counter reaches zero, the shift register contains the required symbol. However, down-counters add cost and complexity to the encoder. Another conventional method is specific to PN code sequences, which may be generated from linear feedback shift registers (LSFRs). The CPM encoded PN code sequence is generated by pre-loading an initial state of the LFSR, the initial state being that corresponding to that which would have been present had the LFSR been started in “all 1s” state, and then clocked 2^ k times.
Conventional solutions that include lookup tables are large, and conventional solutions with circular shift registers require that the code be shifted to its desired state from the last desired state before bit transmission may begin. This requires many clock cycles between the end of transmission of one shifted code, and the next, necessitating the presence of a clock signal that is significantly greater than the shift rate of the PN code. For example, with a 128-chip PN code, it could take up to 64 cycles to shift the register after one code sequence is transmitted, and before the next code sequence is transmitted. Conventional solutions that include the LFSR implementation constrain the PN codes available to members of a small pre-determined set, which are determined by the feedback tap points in the LFSR.
Conventional non-CPM DSSS methods for decoding the circularly shifted symbol include using a correlator to decode the incoming oversampled DSSS signal; however, because CPM encodes most of the date in a bit-shift of the PN code, such a circuit cannot be directly applied to a CPM encoded signal. In order to extract the data encoded in the bit shift, it is necessary to test for a correlation of every possible bit shift of the incoming data in each chip period. Conventional DSSS receivers use a locally generated replica reference PN code (i.e., local code or static code) and a receiver correlator to separate only the desired coded information from all possible signals. The correlator can be thought of as a very special matched filter; it responds only to signal that are encoded with a pseudo noise code that matches its own code. Thus, the correlator can be tuned to different codes simply by changing its local code. This allows the correlator to not respond to man-made, natural, or artificial noise or interference, but only to respond to signals with identical matched signal characteristics and encoded with the identical pseudo noise code. Even if one or more bits in the PN code are damaged during transmission, using a correlator as a statistical technique to extract the original data, the correlator can recover the original data without the need for retransmission. It should be noted that the conventional DSSS receivers devote significant hardware resources to wide, parallel bit-comparisons of samples against the reference code.